A Direct Digital Synthesiser (DDS) typically consists of an n-Bit adder and a clocked register. This arrangement, forming a numerically controlled oscillator or NCO, produces, at time intervals determined by an input clock, a digital number sequence with a periodicity determined by a digital input data signal. The MSB of the digital output represents a digitally controlled synthesized output clock signal.
Advantages of Direct digital synthesizers such as the DDS 100 depicted in FIG. 1 is that they do not use a variable oscillator. Consequently, a DDS has a very fast lock time and very small frequency steps can be selected.
The DDS is essentially a register or accumulator 103 to which a predetermined frequency control value 101 is added on every cycle of an input clock 102. The digital value from the accumulator 103 is often applied to a read-only memory (ROM) 104 that contains sinusoidal output values. The values from the ROM 104 are applied to a digital-to-analog converter 105 and filtered through a low-pass filter 106 to provide an output signal 107 with reduced spurious components. This method requires considerable additional power and its effectiveness is limited to output clock frequencies as determined by the filter characteristics.
A DDS can be reduced to its simplest terms as shown in FIG. 2. The DDS 200 is merely an accumulator 203 to which a frequency control value 201 is added under control of a clock signal 202. The most significant bit (MSB) of the accumulator 203 provides a digital wave output signal 204. Even if one excludes harmonics, however, the DDS 200 will have a high level of spurious signals for many of the possible values of the frequency control word 201, because the output signal instantaneous frequency will change periodically.
As outlined, there are inherent deviations from the ideal that may limit the application of a DDS. The MSB of the DDS output signal is not a spectrally pure signal, because its frequency and “mark-space” ratio are modulated due to discrete sampling by the input clock. This produces timing jitter with maximally 1 clock period duration and a distribution determined by the digital input signal. For a given required output clock frequency, the timing jitter is proportional to the input clock duration, and hence can be optimized by operating the DDS at a high input clock frequency.
This approach requires the NCO to function at a very high speed, and therefore demands complicated adder architectures, adding significantly to power consumption.
Other known methods employ the generation of analog waveforms at predetermined values of the NCO number sequence, and via a comparator generating a digital output signal which is not synchronous with the input reference clock signal. Such an improvement to the simple DDS 200 hereinbefore described is achieved through the analog compensation technique illustrated in FIG. 3. Here, the DDS 300 includes a D-to-A converter 304 at the accumulator output, and the analog voltage at the D/A output is applied to a differential amplifier. A delayed version of the D/A output signal is applied to the other input of the differential amp 305. The differential amplifier 305 provides a square wave pulse train to the integrator 307, which converts the square wave into a sawtooth wave.
The sawtooth waveform is applied to a comparator 308 with a reference voltage 311 at one input. The reference voltage 311 is chosen to be half of the voltage represented by a maximum output from the accumulator 303. The square wave output of the comparator 308 is still asymmetric, but the leading edges occur at intervals with less jitter. If this square wave signal is then applied to a toggle flip-flop 309, the jitter of the output signal 310 will be reduced, and will contain a reduced number of unwanted signals with the exception of the odd harmonics. The notable disadvantage of the DDS 300 of FIG. 3 is that it uses analog techniques to reduce spurious output signals, and similarly to the previous case, this approach requires additional power and its effectiveness depends significantly on maintaining the precision of the analog waveforms for variable input and output.
The advantages of the analog means to reduce the jitter as opposed to techniques that involve the increase of the clocking frequency has resulted in many prior art devices employing predominantly analog means to reduce output signal timing jitter. Unfortunately the usage of an analog solution to the jitter problem suffers from traditional analog problems in that it is more difficult to implement, is non-predictable in its output and is a heavy power consumer. Accordingly, a need arises for a DDS that accomplishes jitter reduction entirely by digital means, and thus avoids parametric variations that plague analog solutions. Such a need has been acknowledged by Goldberg in Chapter four of DDS General Architecture in his book entitled “Digital Frequency Synthesis demystified”, published by LLH Technology Publishing wherein he suggests one solution based on using the carry output bit as an output, and delaying the carry signal so as to effect a more regular interval between transitions. Although this does provide an all digital solution it suffers because it is implemented on the carry signal. The solution described by Goldberg is restricted to the narrow pulse of the carry signal thereby leading to significant unwanted signal components. A reduction of these requires a division of the carry signal frequency by at least a factor of 2, thus reducing the output frequency range. There remains therefore a need for an all digital DDS adapted to achieve reduction of timing jitter over a wide range of input and output clock frequencies using digital data processing without incurring significant increases in complexity and power consumption.